Browse Prior Art Database

Cycle Steal Stacking and Overrun Detection Circuitry

IP.com Disclosure Number: IPCOM000075194D
Original Publication Date: 1971-Aug-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 3 page(s) / 45K

Publishing Venue

IBM

Related People

Brunsvold, DT: AUTHOR [+3]

Abstract

The attachment 10 between a central processing unit (CPU) 12 and a disc file 14 is assigned a lower priority in a system than the attachments for other peripheral devices; and, therefore, cycle steal requests are not always granted by the CPU 12 when requested. The circuitry is operative to remember, in a shift register 16, the cycle steals requested but not granted; and the circuitry also economically detects an overrun condition in buffer 18 in attachment 10.

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Cycle Steal Stacking and Overrun Detection Circuitry

The attachment 10 between a central processing unit (CPU) 12 and a disc file 14 is assigned a lower priority in a system than the attachments for other peripheral devices; and, therefore, cycle steal requests are not always granted by the CPU 12 when requested. The circuitry is operative to remember, in a shift register 16, the cycle steals requested but not granted; and the circuitry also economically detects an overrun condition in buffer 18 in attachment 10.

Data passes from CPU 12 into attachment 10 in bytes of 8 bits and is shifted serially out of attachment 10 to disc file 14 bit-by-bit. Conversely, data from file 14 passes in serial form into attachment 10 from which it passes in 8-bit bytes to CPU 12. In serialize mode for transmission of data to file 14, buffer 18 stores the bytes from CPU 12 for a short time and then transmits them to register 20 from which they are serialized to file 14. Data in the form of serial bits from file 14 enters register 22 from which they are transmitted in 8-bit bytes to buffer 18 for retransmission to CPU 12.

Shift register 16 is a 4-position register which fills with 1's from the left and empties with 0's from the right. The signal "Buffer Data Cycle" on line 24 raises whenever a cycle steal request is granted by CPU 12, and this signal shifts register 16 to the left causing cycle steal request 4 to become 0 and leaving 1's in cycle request positions 1, 2, and 3 in register 16. The subsequent granting of successive cycle steal requests and raising of the signal, Buffer Data Cycle successively puts 0's in cycle request positions 3, 2, and 1 in register 16. The signal "Action Cycle Request" on line 28 is raised when a data byte is being transferred from buffer 18 to one of registers 20 or 22 or vice versa, and at this time buffer 18 can accommodate a cycle steal. The Action Cycle Request signal causes register 16 to be shifted to the right to fill the rightmost position in register 16 having a 0 therein with a 1. Register 16, is thus shifted left one position for each cycle steal granted (indicated by a raising of the Buffer Data Cycle signal), and is shifted to the right one position by the Action Cycle Request signal for each cycle steal requested by CPU 12. This action indicates and stores the difference between the number of cycle steals requested and the number of cycle steals granted by CPU 12. Whenever cycle request 1, li...