Browse Prior Art Database

Dynamic Push Pull Buffer Circuitry

IP.com Disclosure Number: IPCOM000075195D
Original Publication Date: 1971-Aug-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Related People

Lewis, DO: AUTHOR [+3]

Abstract

The circuitry provides two buffers, data buffer 1 and data store 6, between a central processing unit (CPU) 11 and a disk file 12, with the buffers being dynamically loaded and unloaded so as to accommodate disk file 12, which has a high-data rate but a low-cycle steal priority.

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Dynamic Push Pull Buffer Circuitry

The circuitry provides two buffers, data buffer 1 and data store 6, between a central processing unit (CPU) 11 and a disk file 12, with the buffers being dynamically loaded and unloaded so as to accommodate disk file 12, which has a high-data rate but a low-cycle steal priority.

Buffers 1 and 6 consist of two separate groups of memories, each memory consisting of four words of 8 bits plus parity. The words in data buffer 1 are, respectively, words 1, 2, 3, and 4; and the words in data store 6 are, respectively, CC even, CC odd, data store and bit count appendage. Data buffer 1 runs on the clocks and phases of CPU 11 and the data store 6 runs on the time of the disk file 12. The circuitry operates in two modes: a push or deserialize mode taking data from file 12 and pushing it to CPU 11 and a pull mode, pulling data from CPU 11 and serializing it to file 12.

In deserialize mode, read register 3 continuously deserializes data from file 12, and bytes of data are temporarily stored in gate register 4. When action request latch 2 is set, it causes the present push address in counter 9 to be incremented by 1 and then causes the writing of the contents of register 4 into data buffer 1; and the particular word in buffer 1 in which the data is written depends on the incremented value of the address indicated by counter 9. In the case of a first data byte from file 12, the value of the push address increments from 1 to 2, and this first data byte is thus written into word 2 of buffer 1. Cycle request 1 from counter 5 is activated with the rise of the buffer action request line on latch 2; and if CPU 11 were dedicated only to file 12, a data cycle would be granted by CPU 11 immediately. Assuming, however, that interference of other input-output attachments to CPU 11 occurs, a second byte from file 12 accumulates in buffer 1 before a data cycle request can be granted by CPU 11 for file 12. Under these conditions, the second data byte is written into word 3 of buffer 1, which is addressed by the present push address 9. In this cycle, another data cycle request is made and, if granted, gives the next CPU cycle to file 12. When the CPU 11 grants a data cycle, the present pull address counter 10 will be used as the past push address and will be incremented. The counter 10 was initially reset to 1 and is stepped to 2 when the cycle is granted.

The contents of word 2 of buffer 1 will then be transferred to the CPU 11 over DBI bus 14 under control of counter 10. Concurrently, the ne...