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Dynamic Shift Register

IP.com Disclosure Number: IPCOM000075212D
Original Publication Date: 1971-Aug-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Spampinato, DP: AUTHOR

Abstract

Fig. 1 shows a dynamic shift register which operates utilizing the waveforms shown in Fig. 2. The field-effect transistors (FET) Q1-Q4 are N-channel enhancement mode devices. FET device Q1 and diode D1 are shown connected at one of their terminals to phase 1-2 line. The other terminals of these devices are shown connected to a terminal of device Q2; the other electrode of which is connected to node 2. The gate electrode of device Q1 is shown connected to node 1. Device Q3 and diode D2 are shown connected in parallel at one of their electrodes to the phase 1-2 line. The other terminals of these devices are connected to an electrode of FET Q4 while the other electrode of the latter is connected to node 3. The phase 1 and phase 2 lines are shown connected to the gate electrodes of devices Q2, Q4, respectively.

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Dynamic Shift Register

Fig. 1 shows a dynamic shift register which operates utilizing the waveforms shown in Fig. 2. The field-effect transistors (FET) Q1-Q4 are N-channel enhancement mode devices. FET device Q1 and diode D1 are shown connected at one of their terminals to phase 1-2 line. The other terminals of these devices are shown connected to a terminal of device Q2; the other electrode of which is connected to node 2. The gate electrode of device Q1 is shown connected to node 1. Device Q3 and diode D2 are shown connected in parallel at one of their electrodes to the phase 1-2 line. The other terminals of these devices are connected to an electrode of FET Q4 while the other electrode of the latter is connected to node 3. The phase 1 and phase 2 lines are shown connected to the gate electrodes of devices Q2, Q4, respectively. The gate of device Q3 is shown connected to node 2.

In operation, with a positive potential on node 1, the phase 1-2 and phase 1 lines are pulsed to a positive potential at the same time, as shown in Fig. 2, conditionally charging node 2 through diode D1 and Q1 to a positive potential sufficient to turn Q3 ON. Phase 1-2 line is returned to ground (zero volts) conditionally discharging node 2 through ON device Q1. The phase 1 line is then returned to ground completing the cycle. In this manner, the condition of node 2 has been set to the inverse condition of node 1. Thus, a positive potential at node 1 appears as a ground or zero potentia...