Browse Prior Art Database

Shared Remote Control Unit SRCU

IP.com Disclosure Number: IPCOM000075220D
Original Publication Date: 1971-Aug-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 4 page(s) / 59K

Publishing Venue

IBM

Related People

Beard, JN: AUTHOR [+7]

Abstract

The arrangement shown is the program control unit (PCU) of a terminal control unit, which can attach a number of input-output devices to a full-duplex communication channel so that the input-output devices can communicate with a central data processor. The PCU, and its adapters, provide the controls and storage required by each device. The control consists of the manipulation of control signals and data by the use of hardware and a microprogram stored in a control portion of the magnetic core storage. Many of the functions of the control unit, which would normally be performed by hardware, are performed by the micro-code routines.

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Shared Remote Control Unit SRCU

The arrangement shown is the program control unit (PCU) of a terminal control unit, which can attach a number of input-output devices to a full-duplex communication channel so that the input-output devices can communicate with a central data processor. The PCU, and its adapters, provide the controls and storage required by each device. The control consists of the manipulation of control signals and data by the use of hardware and a microprogram stored in a control portion of the magnetic core storage. Many of the functions of the control unit, which would normally be performed by hardware, are performed by the micro-code routines.

The PCU data flow is shown in the drawing. The data flow is dedicated to manipulating and controlling data, commands, status, etc. to meet the requirements of the various I/O adapters. Data is serially transferred between the PCU and the I/O. The high and low bytes of the half-word are transferred simultaneously to yield an effective serial half-word transfer. Data enters the data path via I/O in High, I/O in Low, and exits via Data Out High and Data Out Low. Data may be transferred between the data path and adapters via two modes of operation: share cycle and micro-code control.

A share cycle does not disturb the current micro-instruction in process. The share cycle controls require 3 consecutive memory cycles from the PCU. The first cycle causes a fixed address storage location (SCAW) to be forced into SAR
3. Each I/O adapter, that uses share cycles, has such a fixed address which contains the current running address of the field being utilized by the device. During the second cycle, the address is updated by +2 (bytes). On the third cycle, the address is stored back into the fixed location. The share cycle operation requires 3 memory cycles; however, timing implications extend the total time for a share cycle service to the equivalent of 5 cycles.

During the share cycle, the IAR and GPR's (in local storage 5) in use by the program are left undisturbed in order that the program may continue after the share cycle operation is completed. Micro-code controlled data transfer is accomplished via GET/PUT instructions. In this mode of operation, the program is the controlling element. The I/O devices are addressed by 8 bits in the micro- coded instruction.

The system includes a plurality of registers, each of which contains parity bits for each 8-bit byte. These registers include the following: OPERATION (9) - An 8-bit register which contains

the instruction operation code;

STORAGE ADDRESS (SAR)(3) - A 16-bit register which

contains the address of the data read from or

being written into the core storage unit;

INSTRUCTION ADDRESS (IAR) - A 16-bit register in

Local Storage (5) which contains the address of

the next instruction to be executed;

GENERAL PURPOSE 1-3 (GPR) - Three 16-bit registers

located in Local Storage (5) used by the

1

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microprogram for data/address ro...