Browse Prior Art Database

Instruction Sequence Branch Control

IP.com Disclosure Number: IPCOM000075233D
Original Publication Date: 1971-Aug-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Enger, TA: AUTHOR

Abstract

In large data processing systems having combinations of pipelining, instruction decoding overlap, instruction buffering and prefetching of instruction sequences, it is important to be able to predict when a branch instruction will be encountered. The sequence of instructions, which are the target of the branch instruction should be prefetched so that there is no break in the sequence of instruction decoding and issuing. Branch history tables such as shown in U. S. Patent 3,559,183 have been provided as a means for detecting when a branch instruction is about to be decoded, so that an access can be initiated to storage for the target of the branch instruction.

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Instruction Sequence Branch Control

In large data processing systems having combinations of pipelining, instruction decoding overlap, instruction buffering and prefetching of instruction sequences, it is important to be able to predict when a branch instruction will be encountered. The sequence of instructions, which are the target of the branch instruction should be prefetched so that there is no break in the sequence of instruction decoding and issuing. Branch history tables such as shown in U. S. Patent 3,559,183 have been provided as a means for detecting when a branch instruction is about to be decoded, so that an access can be initiated to storage for the target of the branch instruction.

Entries in the branch history table are made when a branch instruction is first encountered in an instruction sequence. The entry made in the table is the instruction counter value associated with the branch instruction and the address of the target sequence of instructions. Subsequently, as the instruction counter contents are modified, the value is compared with values stored in the branch history table. When a match occurs, an immediate request for access to the target sequence is made utilizing the stored target address. On occasion, the prefetching of the target sequence may have been unnecessary when the branch instruction is a conditional branch and the condition is not met.

The number of times that unnecessary prefetches of target instruction sequences is made can...