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Resolving Store Load Links in a Instruction Unit

IP.com Disclosure Number: IPCOM000075234D
Original Publication Date: 1971-Aug-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Bullions, RJ: AUTHOR [+3]

Abstract

The IBM System/360, as disclosed in U. S. Patent 3,400,371 includes sixteen general purpose registers which can be addressed by at least two different instruction formats. An RX instruction is shown in OP Reg. 1 wherein one operand is designated by four bits of an R1 field specifying a general purpose register. The second operand, to be found in main memory, is addressed by combining a displacement field D with the contents of one of the general purpose registers designated as a base register B, specified by four bits, and an index value found in a general purpose register designated by four binary bits from a field X. Another format of instruction is shown at 2 and is identified as an RR instruction.

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Resolving Store Load Links in a Instruction Unit

The IBM System/360, as disclosed in U. S. Patent 3,400,371 includes sixteen general purpose registers which can be addressed by at least two different instruction formats. An RX instruction is shown in OP Reg. 1 wherein one operand is designated by four bits of an R1 field specifying a general purpose register. The second operand, to be found in main memory, is addressed by combining a displacement field D with the contents of one of the general purpose registers designated as a base register B, specified by four bits, and an index value found in a general purpose register designated by four binary bits from a field X. Another format of instruction is shown at 2 and is identified as an RR instruction. In this instruction format, the operation specified by the operation code will be performed on operands obtained from the general purpose registers specified by the 4-bit R1 field and R2 field.

The additional logic shown is utilized to detect a sequence of instructions wherein data from a general purpose register specified by R1 is to be stored into an address of main memory calculated utilizing the X, B, and D values of an RX instruction. If, subsequent to the storage of the data, another RX instruction specifies that the same memory location should be utilized as one of the operands to be loaded into the system, and the data is still valid in the register designated by the previous Rl field, the instruction will be changed to an RR type instruction wherein the data which would normally be accessed from storage will be accessed from the general purpose register, thus saving the time needed for a reference to memory.

To accomplish this...