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Binary Synchronous Communications Adapter for Microprogrammed Control Unit

IP.com Disclosure Number: IPCOM000075243D
Original Publication Date: 1971-Aug-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 72K

Publishing Venue

IBM

Related People

Houdek, ME: AUTHOR [+3]

Abstract

The binary synchronous communications adapter 10 (BSCA) provides the interface between a microprogrammed control unit 11 (MPU) and a common carrier telephone facility 12 (data set). The BSCA interfaces to the MPU through three 8-bit registers 15, 16 and 17. Register 15 provides a two-way data path 14 to BSCA 10, while control and status lines are assigned to registers 16 and 17.

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Binary Synchronous Communications Adapter for Microprogrammed Control Unit

The binary synchronous communications adapter 10 (BSCA) provides the interface between a microprogrammed control unit 11 (MPU) and a common carrier telephone facility 12 (data set). The BSCA interfaces to the MPU through three 8-bit registers 15, 16 and 17. Register 15 provides a two-way data path 14 to BSCA 10, while control and status lines are assigned to registers 16 and 17.

The BSCA operates asynchronously to MPU 11. The primary timing signal is provided by data set clocks or in the absence thereof, an internal clock. In such case, a BSCA oscillator 18 generates a clock which is in synchronization with the transitions of received data and this derived clock is then the primary timing signal.

The logic of timing circuits 20 combines short MPU pulses with the relatively slow primary timing signal to provide short gate and reset pulses to the BSCA 10. The logic of timing circuits 20 also contains an 8-bit ring counter used to count shifts of the serializer-deserializer 22 (SERDES). Mode select lines 24 are controlled by the microprogram and establish either transmit or receive mode in the adapter. The logic of mode select circuits 26 initiates control lines to data set 12 to establish the corresponding mode. The gating circuits 28 respond to timing pulses and mode signals to generate external gates 30; and the data ready bit, which are transmitted to registers 16 and 17.

In transmit mode...