Browse Prior Art Database

Double Frequency Error Correction

IP.com Disclosure Number: IPCOM000075248D
Original Publication Date: 1971-Aug-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Dix, GL: AUTHOR [+2]

Abstract

This device functions to correct for dropped data bits and dropped clock bits in a double-frequency encoding scheme. The circuit includes a clock (4F clock) which generates a four-times frequency pulse train. The four-times frequency pulse train is re-synchronized at each clock and data bit and since it is continuously running, the clock can stay synchronized if a single clock bit is dropped.

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Double Frequency Error Correction

This device functions to correct for dropped data bits and dropped clock bits in a double-frequency encoding scheme. The circuit includes a clock (4F clock) which generates a four-times frequency pulse train. The four-times frequency pulse train is re-synchronized at each clock and data bit and since it is continuously running, the clock can stay synchronized if a single clock bit is dropped.

Two shift registers P1 through P3 and N1 through N3 are used to store positive and negative transitions under control of the 4F clock. A clock, data, clock sequence is examined. The presence of two positive clock pulses implies that a negative data pulse occurred, and likewise, two negative clock pulses imply a positive data pulse. Thus the presence of two positive or two negative clock pulses implies a one bit. Also, the presence of any data pulse implies a one bit regardless of clock pulses. Therefore, a correction is effected for the loss of a single data or clock pulse.

This scheme may also be extended to correct for single bits erroneously included in a sequence of data and clock pulses.

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