Browse Prior Art Database

Shift Register

IP.com Disclosure Number: IPCOM000075250D
Original Publication Date: 1971-Aug-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 24K

Publishing Venue

IBM

Related People

Hallett, MH: AUTHOR [+2]

Abstract

Shift registers need some form of temporary storage when transferring data from one bit position to another. This circuit uses a relatively slow PNP transistor Q 2 for this purpose. If point A is DOWN, an UP level clock pulse at B forces Q 2 into conduction. When the clock is brought to the DOWN level, Q 1 is cut off and the base of Q 2 is floating. Consequently, Q 2 continues to pass current for a finite time during which the UP level output C can be sampled and transferred by a clock pulse (second phase) to the next bit position. If point A is UP, Q 2 remains cut off during the first clock phase, and the second clock phase transfers the DOWN level at C to the next bit position.

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Shift Register

Shift registers need some form of temporary storage when transferring data from one bit position to another. This circuit uses a relatively slow PNP transistor Q 2 for this purpose. If point A is DOWN, an UP level clock pulse at B forces Q 2 into conduction.

When the clock is brought to the DOWN level, Q 1 is cut off and the base of Q 2 is floating. Consequently, Q 2 continues to pass current for a finite time during which the UP level output C can be sampled and transferred by a clock pulse (second phase) to the next bit position. If point A is UP, Q 2 remains cut off during the first clock phase, and the second clock phase transfers the DOWN level at C to the next bit position.

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