Browse Prior Art Database

Variable Length Timeout Counter

IP.com Disclosure Number: IPCOM000075314D
Original Publication Date: 1971-Sep-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Hinderliter, AR: AUTHOR [+2]

Abstract

In data processing systems where a wide range of time intervals must be determined with substantial precision, the usual use of single-shots is impractical due to the precision requirements and separate timeout clocks are too costly. The clock diagrammed above will enable generation of time intervals of different magnitudes with considerable precision.

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Variable Length Timeout Counter

In data processing systems where a wide range of time intervals must be determined with substantial precision, the usual use of single-shots is impractical due to the precision requirements and separate timeout clocks are too costly. The clock diagrammed above will enable generation of time intervals of different magnitudes with considerable precision.

In the drawing, a crystal oscillator 1 provides the basic timing frequency and the oscillator output is divided in a frequency divider 2 to provide on output lines 3 a group of signals having widely varying repetition rates. A binary counter 4 having denominations 5, 6, 7, 8, etc. is provided to count the pulses in a selected output line 3 and the settings of each of the denominations are transmitted out in a cable 9 to a decoder, where the occurrence of a selected count can be detected. Each output line 3 is one input to a two-input AND gate 10 and is gated through to an OR 11 by a signal on a corresponding gating line 12 on the other input of its AND 10. The output of OR 11 is the counter advancing input to units order counter denomination 5. The signal on each gate line 12 is inverted in its inverter 13 and the outputs of all inverters 13 are connected as inputs to an AND circuit 14 whose output is connected to the reset circuits of all counter denominations 5, 6, etc. This will maintain counter 4 reset when no signals are being gated thereto.

When a time interval is to be measure...