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Browse Prior Art Database

High Speed Latch

IP.com Disclosure Number: IPCOM000075338D
Original Publication Date: 1971-Sep-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Davis, D: AUTHOR [+4]

Abstract

This high-speed latch circuit stores and transfers data onto highly capacitive lines in a minimum time interval of a machine cycle time, thus optimizing "data good" time by minimizing its skew. Additional features include: 1) Stored data that is "glitchless" or isolated from changing input data, 2) Output data in both its true and complemented phases, and 3) The mode of operation of this circuit can be completely changed by removing T5 and keeping all of the above-mentioned features.

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High Speed Latch

This high-speed latch circuit stores and transfers data onto highly capacitive lines in a minimum time interval of a machine cycle time, thus optimizing "data good" time by minimizing its skew. Additional features include: 1) Stored data that is "glitchless" or isolated from changing input data, 2) Output data in both its true and complemented phases, and 3) The mode of operation of this circuit can be completely changed by removing T5 and keeping all of the above-mentioned features.

Both the true and complemented phases of the input data are stored by devices T9 and T10. Data is transferred from the data-in-line to the data-out lines by either charging the bases of T8 and T11 or discharging the bases of T9 and T12. The bases of T8 and T11 are charged when both line #1 and the data- in-line are up, and line #2 is down. The bases of T9 and T12 are discharged with the same logic levels as above with one exception, the data-in line is down. When data is stored, it is isolated from changing input data by holding line #1 down and line #2 up; thus holding the emitter of T7 down and the emitter of T14 up. Transferring data is done in a minimum portion of a machine cycle time by using a feedback current switch, which is physically isolated from the capacitive loading on the data-out line. When turning on devices T8 and T11, feedback of this is done by T13 turning off and thus turning on T9 and T12 independent of the voltage on the data-out line. Discharg...