Browse Prior Art Database

Programmable Logic Chip

IP.com Disclosure Number: IPCOM000075345D
Original Publication Date: 1971-Sep-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Axelrod, MS: AUTHOR [+2]

Abstract

All the features of a Writable Personalized Chip (WPC) can be realized by using conventional read/write memory chips and counters. The counters are added at the periphery of the chip without altering the internal memory structure.

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Programmable Logic Chip

All the features of a Writable Personalized Chip (WPC) can be realized by using conventional read/write memory chips and counters. The counters are added at the periphery of the chip without altering the internal memory structure.

A plurality of X decoders 10, a Y decoder 12, a plurality of read/ write memory cell groups 14, and a read/write control circuit 16 form a conventional 16 x 16 bit memory organization. A modular "16" counter 18 is employed to provide signals to a logic section comprising a plurality of AND gates, and OR gates in order to access each of the separate memory groups 14. A modular "4" counter 20 is employed to provide control signals to the Y decoder 12. A plurality of sense amplifiers 22 provides output signals from each of the 16 columns. Logic input signals are applied to a plurality of terminals labelled X1...X16. The data input line for personalization is connected to the write section of the circuit 16 at terminal 24 in conjunction with a read/write signal being applied at terminal 26. Personalization is accomplished as follows:
1) Set all the logic inputs X1, X2, X3,...to a logical

zero state.
2) Reset counters 18 and 20 entirely to a zero state.
3) Set the read/write control circuit 16 to write.
4) Simultaneously with the step 3 operation, feed data

into terminal 24 in order to perform the write logic.

The first four clock pulses will change the states of counter 20 sequentially to 0, 1, 2, 3 states, respectiv...