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Integrated Circuit Test System

IP.com Disclosure Number: IPCOM000075353D
Original Publication Date: 1971-Sep-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Barnard, JD: AUTHOR [+4]

Abstract

There is provided a computer controlled test system designed to final test large scale integrated circuits. High-speed testing required to functionally test large scale integration is achieved by parallel application of preprogrammed 1 & 0 levels and parallel checking of 1 & 0 output levels against preprogrammed comparison levels on all device I/O pins. However, when it is desired to measure actual output levels, the system (including computer) goes into a closed loop mode measuring one pin at a time.

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Integrated Circuit Test System

There is provided a computer controlled test system designed to final test large scale integrated circuits. High-speed testing required to functionally test large scale integration is achieved by parallel application of preprogrammed 1 & 0 levels and parallel checking of 1 & 0 output levels against preprogrammed comparison levels on all device I/O pins. However, when it is desired to measure actual output levels, the system (including computer) goes into a closed loop mode measuring one pin at a time.

Digital-to-Analog (D-to-A) converters 1 & 2 apply one and zero compare levels to analog compare circuits 8. These levels have been programmed by computer 6 and stored in register 5.

D-to-A converters 3 & 4 (also programmed by computer 6 and stored in register 5) apply one and zero input levels to test pins 7 via analog switches 9.

In both cases the 1/0 (one/zero) registers 10 determine which levels per pin are used - i.e., 1 or 2 and 3 or 4.

I/O switches 11 which can be implemented through relays, solid state switches, or plug board determine Input/Output connections to test pins 7. When test pin 7 is to be an input, I/O switch 11 is closed and the system can perform self-check.

Analog compare 8 gives Go or No/Go output depending on test pin level vs. compare level and status of 1/0 register 10.

Go-No/Go is gated in "A" 12 by the condition of register 13 which has been programmed for pins to be checked. In this manner single pins, all...