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Power Gate Driver Circuit

IP.com Disclosure Number: IPCOM000075354D
Original Publication Date: 1971-Sep-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Cabiedes, A: AUTHOR [+5]

Abstract

The circuit is a TTL compatible, low-standby power, driver circuit for memory applications. The circuit acts as an AND gate, i.e., when all inputs are at the "up" or "1" level, the output is at the up level. It is designed to drive a high-capacitive load. It may be used to pulse power a memory array chip and, therefore, to reduce power on the array.

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Power Gate Driver Circuit

The circuit is a TTL compatible, low-standby power, driver circuit for memory applications. The circuit acts as an AND gate, i.e., when all inputs are at the "up" or "1" level, the output is at the up level. It is designed to drive a high-capacitive load. It may be used to pulse power a memory array chip and, therefore, to reduce power on the array.

With respect to Fig. 1, when all the inputs are at the "1" level, transistors T1, T2 and T3 are in cutoff condition, and transistors T4, T5 and T7 are in saturation therefore holding T9 and T6 in the off condition. In this select condition, the effective circuit is shown in Fig. 2.

Resistor R10 is used to keep T10 very close to saturation preventing oscillation when the circuit is selected. Diodes D7, D8 and D9 establish a selected level for the output. This clamping of the select level permits the circuit to withstand a higher tolerance on the VCC supply. When any of the inputs is in the down level and the circuit is in the nonselect condition, T1 and T2 or T3 saturate driving T4 and T5 into cutoff. T6 turns on and pulls T10 into cutoff. Meanwhile, T9 goes on pulling base charge out of T8 through D6 and discharging load capacitance through D5.

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