Browse Prior Art Database

Storage Cell Using Double Threshold Field Effect Transistors

IP.com Disclosure Number: IPCOM000075359D
Original Publication Date: 1971-Sep-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Kemerer, DW: AUTHOR

Abstract

Considerable reduction in chip space allocation can be achieved through the use of double-threshold field-effect transistors in the four device cell of Fig. 1, which performs the same function as prior six device cells.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 60% of the total text.

Page 1 of 2

Storage Cell Using Double Threshold Field Effect Transistors

Considerable reduction in chip space allocation can be achieved through the use of double-threshold field-effect transistors in the four device cell of Fig. 1, which performs the same function as prior six device cells.

The memory cell comprises cross-connected FETs T1 and T2 and double- threshold FETs T3 and T4 which connect the internal switching nodes 1 and 2 of the memory cell to bit sense lines 3 and 4. The gates of double-threshold FETs T3 and T4 are jointly connected to word line 5. To read or write, the potential on line 5 is raised above the second (higher) threshold of T3 and T4 to permit a proportionally high-sense current to flow. During standby, the potential on line 5 exceeds only the first (lower) threshold of T3 and T4 whereby they function merely as high-impedance load devices for the cross-connected pair of FETs T1 and T2.

Bit lines 3 and 4 and word line 5 are biased to the same relatively low voltage during standby. To read or write, all unselected word lines are reduced to 0 volts, whereas the selected word line is raised to a voltage higher than the standby voltage. The appropriate bit lines are raised in potential during a writing operation, and are recovered to the standby voltage level before the potential on the selected word lines are restored in order not to disturb the unselected cells on the selected bit lines. If desired, the cell may be operated in a lower power mode by no...