Browse Prior Art Database

Self Latching FET Storage Device

IP.com Disclosure Number: IPCOM000075360D
Original Publication Date: 1971-Sep-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 3 page(s) / 61K

Publishing Venue

IBM

Related People

Remshardt, R: AUTHOR [+2]

Abstract

Bistable FET memory cells customarily comprise a cross-connected pair of FETs together with load and accessing devices which usually also comprise FETs. A major reduction in surface area allocation required per memory cell in a monolithic FET memory array can be achieved by the provision of a single FET device having its own bistable (self-latching) operating characteristic.

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Self Latching FET Storage Device

Bistable FET memory cells customarily comprise a cross-connected pair of FETs together with load and accessing devices which usually also comprise FETs. A major reduction in surface area allocation required per memory cell in a monolithic FET memory array can be achieved by the provision of a single FET device having its own bistable (self-latching) operating characteristic.

The FET of Fig. 1 comprises P substrate 10 having two spaced N+ source and drain diffusions 11 and 12, respectively, thin oxide layer 13 and gate metallization 14 to form a well known IGFET structure of the N channel enhancement type. This conventional structure is modified by the provision of conductor 15, which interconnects the gate 14 to the channel region adjacent the pinch off zone Z to impart a self-latching characteristic to the IGFET. If the IGFET is rendered conductive in the usual manner by application of potentials to gate 14 and source and drain 11 and 12, the potential within the channel at the location of conductor 15 is fed back to gate electrode 14 so that the gate potential remains forward biased after the initial gate controlled pulse has subsided. The IGFET remains conductive, as long as operating potentials are applied to source 11 and drain 12 thereby providing a first stable operating condition. In the other stable operating condition, the IGFET is nonconductive. In the nonconductive state, no channel zone is formed between the source and drain, and the gate electrode 14 is maintained simply at the potential of substrate
10.

It is advantageous to maintain gate electrode 14 at a predetermined potential during the nonconductive mode of the IGFET to avoid the possibility of charges, due to leakage currents, causing the gate electrode potential to rise in an uncontrolled manner to a value rendering the IGFET conductive. Increased stability in the nonconductive mode also can be achieved with the aid of the modification shown in Fig. 2. The self-latching IGFET of Fig. 2 corresponds to that of Fig. 1, with the further feature of conductor 16 between gate electrode 14 and the channel region at a point near source 11. Region 16 can be established simultaneously with region 15 by introducing material into openings etched through oxide layer 13 and preferably penetrating slightly substrate 10. Region 16 is smaller in cross-section than region 15, so as to possess significantly higher resistance than region 15.

In operation, a conductive channel is established between source 11 and drain 12 by application of a suitable positive pulse to gate 14. Upon conduction, the channel potential at the position of conductor 15...