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Browse Prior Art Database

FET Delay Circuit Compensated for Device Parameter Variations

IP.com Disclosure Number: IPCOM000075361D
Original Publication Date: 1971-Sep-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Lee, JM: AUTHOR

Abstract

A problem encountered with on-chip delay circuits, whether in bipolar or FET technology, is the large variation of delay as a function of parameter variations over the range of operating temperatures. A substantially constant delay is provided by the multistage delay circuit represented in the drawing through the use of a special reference voltage generator.

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FET Delay Circuit Compensated for Device Parameter Variations

A problem encountered with on-chip delay circuits, whether in bipolar or FET technology, is the large variation of delay as a function of parameter variations over the range of operating temperatures. A substantially constant delay is provided by the multistage delay circuit represented in the drawing through the use of a special reference voltage generator.

Part A of the drawing shows the special reference voltage generator and Part B shows a typical multistage delay circuit characterized by FET land devices T4, T6, T8 and T10 having gates connected to the reference voltage generator, rather than directly to the source of +V. The FET devices are nominally identical to each other, whereby the potential at node 1 is at a point approximately half- way between ground and the supply voltage source +V. The potential of node 1 remains constant regardless of similar parameter variations in FET's T1 and T2; thus, the gate potential of FET T3 is stabilized.

Parameter variations in FET's T4-T11 which tend to increase signal delay at output terminal 2 relative to input terminal 3 also tend to decrease the current through FET T3. A decrease in the current through T3 raises the reference voltage on line 4, which is applied to the gates of FET load transistors T4, T6, T8 and T10. The increase in reference voltage causes a decrease in the signal delay at output terminal 2, which compensates for the aforementioned ten...