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Low Power Dissipation FET Driver Circuit

IP.com Disclosure Number: IPCOM000075362D
Original Publication Date: 1971-Sep-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Lee, JM: AUTHOR [+2]

Abstract

The circuit represented in the drawing is capable of driving large loads, while dissipating relatively little power. In the standby condition, driver transistor T3 is held cutoff and is not dissipating power. During the driving mode, the potential on output line 1 rises rapidly to the potential (+V) of the power source.

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Low Power Dissipation FET Driver Circuit

The circuit represented in the drawing is capable of driving large loads, while dissipating relatively little power. In the standby condition, driver transistor T3 is held cutoff and is not dissipating power. During the driving mode, the potential on output line 1 rises rapidly to the potential (+V) of the power source.

During standby, the input at terminal 2 is up and T1 and T4 are conducting. Nodes A and B are at ground potential and the driver FET T3 is off. When the input signal falls, T1 and T4 are turned off and node A is permitted to rise, charging node B (capacitor C) through T2. T5 remains conducting after T4 is turned off due to the delay circuit 3. Conducting FET T5 holds the output voltage on line 1 at ground potential, while the potential at node B continues to increase. The net result is a rapid rise of the gate-to-source voltage on driver T3.

After the falling input signal passes through delay circuit 3, T5 shuts off and the voltage on output line 1 rapidly rises. The rising voltage is fed back to node B via feedback capacitor C. Resistor R2 enhances the feedback efficiently and is optional. The potential of node B can rise to levels higher than the supply voltage inasmuch as T2 is turned off.

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