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Four Transistor Bipolar Dynamic Shift Register Cell

IP.com Disclosure Number: IPCOM000075371D
Original Publication Date: 1971-Sep-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Jen, TS: AUTHOR

Abstract

This circuit has the capabilities of shifting and storing data in a dynamic form. Transistors T1, T2, T3, and T4 are bipolar transistors. Capacitors C1 and C2 are parasitic collector-to-substrate capacitors.

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Four Transistor Bipolar Dynamic Shift Register Cell

This circuit has the capabilities of shifting and storing data in a dynamic form. Transistors T1, T2, T3, and T4 are bipolar transistors. Capacitors C1 and C2 are parasitic collector-to-substrate capacitors.

Input data is applied to the base of transistor T2. Initially, 01 control signal is applied to the base of transistor T1. Capacitor C1 is charged to an up level through the base-to-collector diode of T1. 02 control signal is then applied to the emitter of transistor T2.

When the input data at node 10 is at the up level, transistor T2 will be turned into conduction. T1 will be turned into conduction subsequently. Switching 01 from the up level to the down level during this time will discharge C1 to a down level. Control signal 03 is then applied to the base of transistor T3. This will charge capacitor C2 to the up level. Control signal 0 4 is then applied to the emitter of transistor T4. T4 will not conduct because node 14 is at the down level. 03 is returned at this time from the up level to the down level. The voltage at node 18 will not change because of no conduction. The output data is therefore at the up level.

When the input data at note 10 is at the down level, the application of 02 will not turn on T2. The voltage at node 14 will remain at the up level at the completion of applying 01 and 02. The application of 04 will therefore turn T4 into conduction. T3 will be turned into conduction also. C2 will...