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Parity Prediction Circuitry for Cyclic Code Checking

IP.com Disclosure Number: IPCOM000075398D
Original Publication Date: 1971-Sep-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Miller, TH: AUTHOR [+2]

Abstract

The parity-prediction circuitry operates for both the read and write modes of file 12. In the read mode, data from file 12 is read therefrom in serial fashion and is transmitted to CPU 10 in bytes; and in the write mode, data from CPU 10 is pulled therefrom in bytes and is serialized for writing on file 12. In both cases, a new data word that is transmitted to either file 12 or CPU 10 is included in a check byte, and will be located in read register 1 during the beginning of the data byte time following the time at which the byte was transmitted to either file 12 or CPU 10. Cyclic Check (CC) bytes are accumulated and are stored in data store 2, and the circuitry begins with a CC odd byte and then alternates between CC odd bytes and CC even bytes, forming a 16-bit cyclic check character in the two words of store 2.

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Parity Prediction Circuitry for Cyclic Code Checking

The parity-prediction circuitry operates for both the read and write modes of file 12. In the read mode, data from file 12 is read therefrom in serial fashion and is transmitted to CPU 10 in bytes; and in the write mode, data from CPU 10 is pulled therefrom in bytes and is serialized for writing on file 12. In both cases, a new data word that is transmitted to either file 12 or CPU 10 is included in a check byte, and will be located in read register 1 during the beginning of the data byte time following the time at which the byte was transmitted to either file 12 or CPU 10. Cyclic Check (CC) bytes are accumulated and are stored in data store 2, and the circuitry begins with a CC odd byte and then alternates between CC odd bytes and CC even bytes, forming a 16-bit cyclic check character in the two words of store 2.

Initially, the line "CC Odd Select" selects the CC odd word from data store 2. This byte is valid at the input of the Exclusive-OR register 3 during the first portion of byte time 2, the transmission of the initial byte having taken place during byte time 1. The output of XOR register 3 is equal to the Exclusive-OR of the read register 1 containing the first data word to be transmitted to either file 12 or CPU 10 and the CC odd word from store 2, which is the old CC odd byte. The Exclusive-OR output value which is the new CC byte is flushed through gate register 4 and is written back into data store 2 in place of the old CC odd byte. For successive data bytes, the same process is repeated with CC even and CC odd being alternately selected from data store 2. The ninth or parity bit (carried by line "Predicted Parity") of the...