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Unidirectional Charge Coupled Shift Register

IP.com Disclosure Number: IPCOM000075454D
Original Publication Date: 1971-Sep-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Anantha, NG: AUTHOR [+3]

Abstract

This shift register utilizing charge-coupled devices has improved charge transfer efficiency and is capable of operation with two clock lines. The shift register has a semiconductor body 10 lightly doped with an N impurity, two P+ diffusions 11 and 12, a plurality of N diffused regions 13, 14, 15, and 16, a plurality of doped polysilicon gates 17, 18, 19, 20, and 21, a charge injection terminal 22, a first clock line 23 and a second clock line 24. Each of metal terminals 25 make contact with the adjacent polysilicon gate. Any number of diffusion regions and gate combinations between 22 and 26 can be used.

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Unidirectional Charge Coupled Shift Register

This shift register utilizing charge-coupled devices has improved charge transfer efficiency and is capable of operation with two clock lines. The shift register has a semiconductor body 10 lightly doped with an N impurity, two P+ diffusions 11 and 12, a plurality of N diffused regions 13, 14, 15, and 16, a plurality of doped polysilicon gates 17, 18, 19, 20, and 21, a charge injection terminal 22, a first clock line 23 and a second clock line 24. Each of metal terminals 25 make contact with the adjacent polysilicon gate. Any number of diffusion regions and gate combinations between 22 and 26 can be used.

The potential well created by a surface electrode is not as deep under the metal gate 25 than under the polysilicon gates 17 through 21. By a suitable application of three clock pulses to clock lines 23 and 24, a charge can be caused to move to the right and finally be sensed at terminal 26. A clock potential level V1 can be selected having a level wherein a potential well exists only in the N- regions beneath the polysilicon gates, a second potential V2 at which the potential well vanishes, and a third potential V3 at which the potential wells exist in both the N and N- regions, that is under the electrode 25 and polysilicon gate. By proper application of clock pulses V1 through V3 to clock lines 23 and 24, charges can be transferred from the first to the third potential well. Thus, two potential wells per bit with t...