Browse Prior Art Database

Logic Card Tester

IP.com Disclosure Number: IPCOM000075460D
Original Publication Date: 1971-Sep-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Krosner, SP: AUTHOR [+3]

Abstract

An automatic test system for logic cards, having a wide variety of logic circuit networks, can employ data processing program techniques to generate test patterns tailored to the individual cards, and can utilize data processing logical apparatus to employ the patterns to test each card, to indicate test failures, and to aid in diagnosis of the cause of a failure.

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Logic Card Tester

An automatic test system for logic cards, having a wide variety of logic circuit networks, can employ data processing program techniques to generate test patterns tailored to the individual cards, and can utilize data processing logical apparatus to employ the patterns to test each card, to indicate test failures, and to aid in diagnosis of the cause of a failure.

Where the cards to be tested have been made in accordance with automated or semiautomated design techniques, the character and relationship of the logical elements in the card may already be available in the form of records stored in computer tape 20 or other data storage devices. These records can be fed to computer 22 and operated upon, in accordance with a test pattern generation program previously loaded from 24. The program is designed to order the path element relationships between input and output pins of the card, to recognize feedback loops within the card and, using this information, to determine the outputs which will be characteristic of a good card when the inputs of the card are energized in a prescribed manner.

The input test signals are specified by the program to include as many sequentially applied patterns as are necessary to test for all of the possible failure modes of operation of the card to be detected. The test patterns consist of up and down levels to be applied to each of the input pins and to be expected at each of the out pins, together with the time delays between the two which are characteristic of a good card. These test patterns generated by computer 22 are loaded via 26 into a buffer-controller 28, which feeds the required patterns sequentially to the card tester 30.

Tester 30 resp...