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Integrating NbO(x) Switch Array with FET Read/Write Circuits

IP.com Disclosure Number: IPCOM000075477D
Original Publication Date: 1971-Sep-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 3 page(s) / 40K

Publishing Venue

IBM

Related People

Kircher, CJ: AUTHOR [+2]

Abstract

The methods shown replace a niobium-silicon diode with a diffused PN junction diode in integrated niobium oxide switchable resistor (NOSR) arrays with field-effect transistor (FET) read/write circuitry. In addition to taking advantage of the more reliable reverse characteristics of these diodes, a much lower series resistance is obtained by using a buried layer "Y" line with much lower sheet resistance (15 ohms per square).

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Integrating NbO(x) Switch Array with FET Read/Write Circuits

The methods shown replace a niobium-silicon diode with a diffused PN junction diode in integrated niobium oxide switchable resistor (NOSR) arrays with field-effect transistor (FET) read/write circuitry. In addition to taking advantage of the more reliable reverse characteristics of these diodes, a much lower series resistance is obtained by using a buried layer "Y" line with much lower sheet resistance (15 ohms per square).

Referring to Figs. 1-3, a typical process sequence for the fabrication of P- channel FETs is shown. Fig. 1 shows a silicon wafer 1 of P conductivity type which has a resistivity of 2 ohm-centimeters. Diffusion windows 2 formed in silicon dioxide layer 3 by conventional photolithographic and etching techniques permit the diffusion of N+ conductivity type regions 4, which form "a buried layer" for FET pockets and "Y" lines. Diffusions 4 are carried out by conventional techniques.

After diffusing, the remaining silicon dioxide regions 3 are stripped and an epitaxial layer 5 of P conductivity type semiconductor material, having a resistivity of 2 ohm-centimeters, is grown on the surface of silicon wafer 1 by conventional techniques. A layer 6 of silicon dioxide is grown on epitaxial layer 5 and an out-diffusion of buried layers 4 is carried out, to provide 2 ohm-centimeter N-type regions in epitaxial layer 5. This provides the proper channel resistivity for the subsequently formed FETs.

Fig. 3 shows windows 7 formed in layer 6 by conventional photolithographic and etching techniques. Source and drain regions 8 and 9, respectively, and NOSR regions 10 are formed by diffusing P conductivity type material into openings 7 to a depth that will result in a P+/N junction where N(D) is 1017 donor atoms/cm . This results in the desired breakdown voltage for the NOSR diode. Silicon dioxide layer 11 is then regrown over openings 7 and a complete FET, not shown, is formed using conventional steps.

Referring to Fig. 4, there is shown therein a cross section of a Niobium Oxide Switchable Resistance (NOSR) and diode element at the intersection of an X and Y line. In Fig. 4, diffused regions 10 and 4 form a PN junction diode which has been fabricated as indicated hereinabove in connection with Figs. 1-3. Using conventional photolithographic and etching techniques, a window 11 is formed in silicon dioxid...