Browse Prior Art Database

Ternary Read Only Memory

IP.com Disclosure Number: IPCOM000075505D
Original Publication Date: 1971-Sep-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Maley, GA: AUTHOR [+2]

Abstract

A read-only memory for use in a three-valued logic system may be constructed so that it is read for one of three impedance values at each of a matrix of bit positions: a diode D, a shunt S, or an open circuit.

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Ternary Read Only Memory

A read-only memory for use in a three-valued logic system may be constructed so that it is read for one of three impedance values at each of a matrix of bit positions: a diode D, a shunt S, or an open circuit.

The figure shows three of a matrix row of bit positions formed by transistors T7, T8, T9 and their respective impedances between their emitter terminals 14, 15, 16 and terminals 18, 19, 20 of line 21. Since each of the three bit positions can be wired for any one of three impedances, twenty-seven different combinations can be formed. Accordingly, the three illustrated bit positions can, in combination, store a complete decimal digit.

Each matrix row is provided with a word amplifier 22, which is capable of translating the impedance detected at a bit position into a level of current flow through load resistor R3 and finally into one of three voltage levels at output 26.

In reading the stored ternary bits, one of bit inputs 11, 12 and 13 and word input 23 are switched between 0 and 2. To read the "2" ternary bit, bit line 12 is energized to 2-level and word input 23 is dropped to the 0-level, so that both T3 and T4 are cut off by shunt S. Two units of current {one from T1 and one from T2 via diode 28} flow through T8, while no current flows through R3. Lead 24 and hence output 26 will be at their highest level to indicate a ternary "2" at 26.

If lines 11 and 23 are energized to open T7 and close T3, only one unit of current flows thro...