Browse Prior Art Database

Self Restoring Six Device FET Memory Cell

IP.com Disclosure Number: IPCOM000075507D
Original Publication Date: 1971-Sep-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Baitinger, U: AUTHOR [+3]

Abstract

The memory cell consists of six field-effect transistors (FET's) and is so designed that the written information is not destroyed after the cell has been in the stand-by state for a longer period of time.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 82% of the total text.

Page 1 of 2

Self Restoring Six Device FET Memory Cell

The memory cell consists of six field-effect transistors (FET's) and is so designed that the written information is not destroyed after the cell has been in the stand-by state for a longer period of time.

FET's T1 and T2 are cross-coupled and form the bistable multivibrator cell. FET's T3 and T4 are employed as control means and are connected, via their gate, to a word line WL, via their drain, to bit lines BO and B1, and, via their source, to nodes N1 and N2.

In the stand-by state of the cell, leakage currents cause a discharge in the cell capacities on nodes N1 and N2, so that the information is avoided by a suitable recharging current being continuously applied to nodes N1 and N2 via FET's T5 and T6 connected to the voltage source V and which are used as load devices.

As the load devices only have to replenish leakage currents in the nanoampere range, their resistivity can be high and their tolerance limit wide.

Considering that the threshold voltage of an enhancement mode MOSFET (normally off) decreases as the channel length is reduced and in some cases is less than zero and that the effective drain source currents suffice as recharging currents even for gate source voltages below the threshold voltage, two embodiments result for the design and the circuitry of load devices T5 and T6.

The two gates of T5 and T6 can be grounded (dotted line) or the gates of the two FET's are linked to the source. To ensure the required...