Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Capacitive Load Driver

IP.com Disclosure Number: IPCOM000075528D
Original Publication Date: 1971-Oct-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Esteban, DJ: AUTHOR

Abstract

The circuit is intended to drive high-capacitive loads at high frequencies. It is comprised of a complementary NPN-PNP transistor output stage (T2, T3) bootstrapped by capacitor K2, a common-base driving stage T1 controlled by a diode-capacitor circuit D1, K1, and a drive input controlled by the data.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Capacitive Load Driver

The circuit is intended to drive high-capacitive loads at high frequencies. It is comprised of a complementary NPN-PNP transistor output stage (T2, T3) bootstrapped by capacitor K2, a common-base driving stage T1 controlled by a diode-capacitor circuit D1, K1, and a drive input controlled by the data.

Whenever the drive input is low, capacitor K1 is charged to E1 through diode D1. Then T1 is turned off due to reverse biasing of its base by D1. At the same time, T2 is turned on through resistor R2 and capacitor K2 which has been previously charged to E1+E2. Load capacitor CL is therefore charged to E2 through transistor T2.

Whenever the drive input is high T1, is forward biased by a current source from K1. Then T3 is turned on and capacitor K2 is charged to E1+E2 Load capacitor CL is therefore charged to El through transistor T3.

Thus the device output swings between levels E1 and E2 in accordance with the drive input level.

1

Page 2 of 2

2

[This page contains 2 pictures or other non-text objects]