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Buffer Management in a Multitasking Environment

IP.com Disclosure Number: IPCOM000075540D
Original Publication Date: 1971-Oct-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 3 page(s) / 76K

Publishing Venue

IBM

Related People

Wescott, JL: AUTHOR

Abstract

This general buffer management scheme shown in Fig. 1 handles buffers in an input-process-output situation. Single and double buffering in varying combinations for any number of I/O devices are supported. It operates on a buffer complex defined for each device. System Support Requirements: 1) Multitasking. Basic to this buffer management scheme is a multitasking environment in which the major functions of input, processing and output are asynchronous tasks. 2) Queued Wait. The queued wait list is a control program facility, which allows event control block (ECE) elements to be chained off a queue header. Adding an element to a chain involves the two separate steps of routing the ECB to the appropriate list header and issuing the POST command to add the ECE to the list.

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Buffer Management in a Multitasking Environment

This general buffer management scheme shown in Fig. 1 handles buffers in an input-process-output situation. Single and double buffering in varying combinations for any number of I/O devices are supported. It operates on a buffer complex defined for each device. System Support Requirements: 1) Multitasking. Basic to this buffer management scheme is a multitasking environment in which the major functions of input, processing and output are asynchronous tasks. 2) Queued Wait. The queued wait list is a control program facility, which allows event control block (ECE) elements to be chained off a queue header. Adding an element to a chain involves the two separate steps of routing the ECB to the appropriate list header and issuing the POST command to add the ECE to the list. Retrieval of an ECB is accomplished by the WAITQ command which unchains the element from the specified list on first-in-first-out basis and returns the element address in a register. When the list has no elements, the requesting task is put into the wait state. 3) Basic Input/Output Control System (IOCS). An I/O control system at the basic, unqueued level is required for both input and output. I/O completion must be signaled by IOCS with a POST which is compatible with a user-issued POST. 4) Input Data Event Control Blocks (RDECB) and Output Data Event Control Blocks (WDECB) of Fig. 2 are tables which describe the I/O operation currently in process. It is posted by the IOCS component at the completion of I/O.

Program Support Requirements - Several control blocks are required to record the status of the I/O buffers. 1) Central Control Block of Fig. 3 is a table, which defines the entire I/O buffer complex for an output device. 2) Input Buffer Event Control Block (IBECB) and Output Buffer Event Control Block (OBECB) of Fig. 2 are tables which define the status and availability of each I/O buffer. They are the communication between asynchronous tasks.

Initialization Requirements - The buffer management logic is unaware of the number and configuration of I/O devices and I/O buffers to be supported. It is assumed that the necessary control blocks were generated and initialized prior to entering the I/O processing cycle. RDECB's and IBECB2's, if present, are flagged as being available to the read task. All OBECB's are flagged as being available to the processor task. WDECB's are flagged as being available to the write task. IBECB1's are posted to the read task to initiate the I/O cycle.

Read Task - The read task reads data from the input device and posts the full buffers to the processor task when I/O has successfully completed. It is driven by a queued resource list which contains IBECB's and RDECB's. An IBECB represents an empty input buffer for which I/O is to be started, and an RDECB represents completed I/O for which the full input buffer is to be posted to the processor task.

When the processor task empties an input bu...