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Tester Programmed by Responses of Test Devices to Prior Interrogation

IP.com Disclosure Number: IPCOM000075545D
Original Publication Date: 1971-Oct-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 3 page(s) / 49K

Publishing Venue

IBM

Related People

Schlemmer, P: AUTHOR

Abstract

The trend toward larger levels of circuit integration and complexity and the proliferation of different types of integrated circuits, increasingly tax the techniques used for testing large integrated circuit arrays. Large scale integrated computer logic circuits can be tested reliably without the need for individualized testing programs specifically designed for each circuit, through the expedient of statistical testing techniques.

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Tester Programmed by Responses of Test Devices to Prior Interrogation

The trend toward larger levels of circuit integration and complexity and the proliferation of different types of integrated circuits, increasingly tax the techniques used for testing large integrated circuit arrays. Large scale integrated computer logic circuits can be tested reliably without the need for individualized testing programs specifically designed for each circuit, through the expedient of statistical testing techniques.

The tester represented in the drawing applies a set of input signal patterns to a significant sample quantity of integrated logic circuit chips of the same type. The resulting signal outputs, which comprise a mixture of "correct" and "error" responses are monitored and recorded for each chip in the sample group. Inasmuch as the sample group is selected from actual product, the monitored and recorded outputs reflect real product technological and topological factors (such as on-chip reactances, fan-out and form factors). The responses for each pin are statistically examined for all the sample chips tested, and predictable responses are distinguished from nonpredictable responses on the basis of the frequency with which a given response recurs. The proper responses are then used by the tester in checking all of the product chips represented by the tested sample chips.

Pattern generator 1 provides a number of available input signals which are selected by punch card controlled switches 2 for application to respective input pins of integrated circuit chip 3, which is one from a sample quantity representing a large number of product integrated circuit chips to be tested. The output pins of the device 3 are connected to respective identical statistical examining channels 4, 5 and 6. Each channel includes a punch card controlled load selector 7, an output up-level signal detector 8, an output downlevel signal detector 9, punch card controlled inhibit switches 10 and 11, a response counter 12, and an output signal level fail detector 13. Selectors 2 and 7 are controlled by a first punch card, which is determined before the start of the sample test. Switches 10 and 11 are controlled by a second punch card, which is determined in accordance with the results of the sample test.

Each chip from the sample quantity is exercised by test pattern generator 1, and the total number of output levels passing the uplevel signal detectors 8 are counted by one of the counters 12 for each pin in response to each test pattern. A large number of different test patterns are applied so that each output pin generally provides many responses. Most of the responses are within predetermined acceptable voltage limits, while some responses associated with defective outputs may be outside acceptable limits...