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Transistor Samples for Microscopic Study

IP.com Disclosure Number: IPCOM000075550D
Original Publication Date: 1971-Oct-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Kulkarni, MV: AUTHOR [+4]

Abstract

A method has been developed for preparing ultrathin (less than 1 micron thick) electron microscope samples of small transistors, having dimensions in the micron range. The method of thinning the silicon samples may be successively used to isolate a single transistor from an integrated circuit and thin it down to the proper thickness. The method takes advantage of a basic configuration of integrated circuits where the transistors or other active elements are usually electrically isolated from each other by the use of isolation diffusions, which extend all the way to substrate silicon wafer. P- silicon wafers and P+ isolations are used in the case of NPN type transistors.

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Transistor Samples for Microscopic Study

A method has been developed for preparing ultrathin (less than 1 micron thick) electron microscope samples of small transistors, having dimensions in the micron range. The method of thinning the silicon samples may be successively used to isolate a single transistor from an integrated circuit and thin it down to the proper thickness. The method takes advantage of a basic configuration of integrated circuits where the transistors or other active elements are usually electrically isolated from each other by the use of isolation diffusions, which extend all the way to substrate silicon wafer. P- silicon wafers and P+ isolations are used in the case of NPN type transistors.

As illustrated, the method involves electrochemical thinning. In this method the oxides on such a wafer are first removed. The front and back of the surfaces are then covered with black wax, leaving uncoated an approximately one square centimeter area on the back of the wafer opposite the transistor to be etched out. After establishing an electrical contact to the substrate silicon wafer, the wafer is made an anode in the electrolytic cell containing a 5% HF aqueous solution (as an electrolyte) containing a large area platinum cathode. The electrolysis is continued at a current density of about 0.025 amp/cm2, until the substrate silicon and isolation regions around the transistor are completely dissolved anodically. On completion of the electrolysis, the tr...