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Browse Prior Art Database

Three Device MOSFET Charge Storage Cell

IP.com Disclosure Number: IPCOM000075556D
Original Publication Date: 1971-Oct-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 21K

Publishing Venue

IBM

Related People

James, RP: AUTHOR

Abstract

In this storage cell only two address lines are required for addressing, which results in a reduction of the cell area.

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Three Device MOSFET Charge Storage Cell

In this storage cell only two address lines are required for addressing, which results in a reduction of the cell area.

In most conventional MOSFET memory cells three or more address lines are normally required. One exception is the capacitor stored charge cell which requires only two. This cell has a number of drawbacks namely the read-out is destructive, the stored charge redistributes between the cell and the bit line capacitance, and the writing speed is limited by the information storage capacitor which must be made large enough to yield a reasonable sense charge.

In this cell data is stored as a charge on the capacitance of the gate of T3 and the source of T1. To write into the cell on a selected word line, the word line is raised to +10 volts to turn on T1. A "1" is stored in a cell by raising the bit line to +10 volts, thereby charging the cell to storage capacitance to about +8.65 volts. To store a "0" the bit line is held at 0 volts so that the storage capacitance is left uncharged. Previously stored data is retained in an unselected cell by holding the unselected line at 0 volts, thereby holding T1 off and retaining any charge on the storage capacitance. To read the cell on a selected word line, the word line is raised to +2 volts thereby turning on T2. If a 1 is stored in the selected cell, T3 is also on so that the current flows from the bit line to the ground. If a 0 is stored, T3 is off and no current flows f...