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TTL Circuit for Driving Heavy Load

IP.com Disclosure Number: IPCOM000075557D
Original Publication Date: 1971-Oct-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Wiedmann, SK: AUTHOR

Abstract

TTL circuits with an active pull-up transistor at the output provide a fast charging-up of the load capacitance, when the gate is switched into its uplevel state. The disadvantage of these circuits are: 1) During the switching transient, an additional large power supply current is flowing because both output transistors are conducting simultaneously. 2) The turn-off current of the grounded output transistor is limited by the discharge resistor connected between base and ground. (Similarly to a conventional DTL gate). This circuit overcomes these two disadvantages without adding circuit complexity. Instead of a single transistor phase splitter, a current switch circuit T2, T4 is used to drive the output transistors.

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TTL Circuit for Driving Heavy Load

TTL circuits with an active pull-up transistor at the output provide a fast charging-up of the load capacitance, when the gate is switched into its uplevel state. The disadvantage of these circuits are:
1) During the switching transient, an additional large

power supply current is flowing because both output

transistors are conducting simultaneously.
2) The turn-off current of the grounded output transistor

is limited by the discharge resistor connected between

base and ground. (Similarly to a conventional DTL gate). This circuit overcomes these two disadvantages without adding circuit complexity. Instead of a single transistor phase splitter, a current switch circuit T2, T4 is used to drive the output transistors. The reference voltage (preferably derived on the same chip) is chosen approximately 100---200mV below the threshold VBE of T1, which is typically 0.75V.

This circuit substantially avoids the situation where both output transistors T1 and T3 are conducting simultaneously. It also provides a fast turn-off operation of T1, since a large discharge current will flow into the collector of T5 when one of its emitters (input terminals) has been returned to OV.

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