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On Chip Redundancy Scheme

IP.com Disclosure Number: IPCOM000075607D
Original Publication Date: 1971-Oct-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 3 page(s) / 48K

Publishing Venue

IBM

Related People

Schuster, SE: AUTHOR

Abstract

This circuit relates to a technique for implementing a redundancy scheme, which requires only one additional reset line in the X and Y directions and two types of decoder circuits. The additional reset lines and decoders make it possible to replace a bad word or bit line (or decoder) with a given address, with another word or bit line (or decoder) and still utilize the same address. The selected decoder is disabled by the use of its own output. The information necessary for this substitution is stored in latches on the chip. The complexity of the decoders does not change as the number of lines to be replaced increases.

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On Chip Redundancy Scheme

This circuit relates to a technique for implementing a redundancy scheme, which requires only one additional reset line in the X and Y directions and two types of decoder circuits. The additional reset lines and decoders make it possible to replace a bad word or bit line (or decoder) with a given address, with another word or bit line (or decoder) and still utilize the same address. The selected decoder is disabled by the use of its own output. The information necessary for this substitution is stored in latches on the chip. The complexity of the decoders does not change as the number of lines to be replaced increases.

A memory formed on a semiconductor chip which contains an array of M x N storage positions organized on a bit basis, and which also includes spare bit and word lines utilizes the decoders shown in Figs. 1 and 2. In addition to the X and Y-decode lines normally present, one additional X Reset line and one additional Y Reset line is needed. The number of spare word and bit lines added depends principally on the defect density. The decode circuits of Figs. 1 and 2 afford the ability to dynamically replace bad word and bit lines.

The circuit entitled Type 1 Decoder is a standard FET decoder, plus a latch and a number of additional devices that operate as follows:

When one or more bad bits associated with a particular bit or word line is present, FET 1 is turned ON permanently. This is accomplished by energizing the Reset line when the decode FETs (2, 3, 4, 5) are addressed in the usual manner, by applying address line inputs to the gates of the decode FETs. For a given word or bit line, the Decode circuitry selects it when all the decode FETs (2-5) are in the OFF or nonconducting condition. When this occurs, a high potential appears at node N1. This potential is fed back via feedback path 6 and FET 7 to apply a low potential via c...