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Reset of Shift Register Counters

IP.com Disclosure Number: IPCOM000075613D
Original Publication Date: 1971-Oct-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Southworth, RA: AUTHOR

Abstract

It is desirable to use minimum area shift register circuits for counting functions on a L S I MOSFET chip. The problem is initializing these counters to a known state without increasing their area and, therefore, decreasing the amount of logic that may be packed on a chip.

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Reset of Shift Register Counters

It is desirable to use minimum area shift register circuits for counting functions on a L S I MOSFET chip. The problem is initializing these counters to a known state without increasing their area and, therefore, decreasing the amount of logic that may be packed on a chip.

A counter may be implemented from N shift register circuits that will step through 2/N/ - 1 states in a predetermined sequence (not binary). These counters are well described in the literature and are commonly referred to as maximum length sequence shift register counters. They are especially well suited for MOSFET technology, because the shift register circuit requires less than half the area of a binary trigger.

To retain all of the area advantage, it is necessary to design the shift register circuit with no reset input. However, to be useful, a counter must be initialized to a known state.

Illustrated is a counter and reset control. The contents of each register stage are sampled by the NAND I. When any stage contains a "0" the output of the NAND 1 is "1" which causes the latch to apply a 0 to the NAND 2, which in turn outputs 1's to the shift register. To reset the counter, a reset pulse is applied for one clock cycle to the inverter which causes a 0 level to be applied to the latch, which outputs a 1 for one clock cycle to NAND 2. The 0 level from the inverter is also applied to NANDS 3 and 4, causing them to output 1's to NAND 2. Since all three inputs to...