Browse Prior Art Database

Fabrication of Self Aligned IGFET Devices With Continuous Oxide in Thin and Thick Regions

IP.com Disclosure Number: IPCOM000075634D
Original Publication Date: 1971-Oct-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Kaplan, LH: AUTHOR [+3]

Abstract

In conventional FET fabrication, thin gate oxide and thicker diffusion masking oxide are grown in separate oxidation operations.There is evidence that gate shorts can occur, where gate metallurgy passes over the step where the thin gate oxide abuts the thicker masking oxide layer. Figs. 1-8 show a process for making self-aligned gate IGFET devices, having a continuous layer of thin oxide forming the gate insulating layer and covering all other (nongate) areas as well. The thickness of the continuous oxide is selectively increased in the nongate areas.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 61% of the total text.

Page 1 of 2

Fabrication of Self Aligned IGFET Devices With Continuous Oxide in Thin and Thick Regions

In conventional FET fabrication, thin gate oxide and thicker diffusion masking oxide are grown in separate oxidation operations.There is evidence that gate shorts can occur, where gate metallurgy passes over the step where the thin gate oxide abuts the thicker masking oxide layer. Figs. 1-8 show a process for making self-aligned gate IGFET devices, having a continuous layer of thin oxide forming the gate insulating layer and covering all other (nongate) areas as well. The thickness of the continuous oxide is selectively increased in the nongate areas. The technique not only lessens the problem of gate shorts at thin-to-thick oxide steps, but also reduces gate oxide contamination during subsequent processing, gate pinholes or contamination occurring at contact hole opening, undercutting at gate oxide opening, and large gate-diffusion overlap.

No autodoping of the gate oxide by the thick doped oxide regions is possible.

In Fig. 1, gate oxide 1 is grown on P silicon wafer 2 and silicon nitride 3 is deposited on oxide 1. A source-drain diffusion mask is applied and source and drain diffusion holes 4 and 5, respectively, are opened in nitride layer 3, as shown in Fig. 2. Source and drain dopant is deposited into and through areas 6 and 7 of oxide layer 1, the silicon nitride 3 masking the dopant from all other areas of oxide 1 (Fig. 3).

A gate mask is applied to protect the silic...