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Man Machine Test Pattern Generator System

IP.com Disclosure Number: IPCOM000075639D
Original Publication Date: 1971-Oct-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Carpenter, RG: AUTHOR [+2]

Abstract

In our paper entitled "Man-Machine Test Pattern Generator", presented at the IEEE Convention in New York City, in March 1969, and published in the Convention Digest, on pages 380-381, session 8B: Graphics and Computer Aided Design, paper 8B.1, we described a test pattern generator involving the use of an IBM 1130 computer in combination with an IBM 2250 Graphic Display Unit. In this system, the logic blocks and nodes in the circuit network are displayed on the screen of the IBM 2250. Then, by means of a light pen, the input points in the circuit, which represent the input pins, are biased at either the "1" or "0" level to simulate an input pattern increment.

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Man Machine Test Pattern Generator System

In our paper entitled "Man-Machine Test Pattern Generator", presented at the IEEE Convention in New York City, in March 1969, and published in the Convention Digest, on pages 380-381, session 8B: Graphics and Computer Aided Design, paper 8B.1, we described a test pattern generator involving the use of an IBM 1130 computer in combination with an IBM 2250 Graphic Display Unit. In this system, the logic blocks and nodes in the circuit network are displayed on the screen of the IBM 2250. Then, by means of a light pen, the input points in the circuit, which represent the input pins, are biased at either the "1" or "0" level to simulate an input pattern increment. In this fashion, the above- mentioned publication permits the operator to apply various increments in a signal pattern and to observe the resulting output at a plurality of output points in the circuit simulation.

In the circuit described, it is possible, by the use of the light pen in a similar fashion, to bias at the 1 or 0 level various nodes within the display circuit, in addition to biasing the input points or pins. In this fashion, conditions can be simulated wherein various points in the circuitry to be tested are stuck at either the 1 or 0 conditions. Such a "stuck" condition is a logic failure. With such a capability, tests can be designed which will detect such stuck conditions.

This is done in the following manner: a given node in the circuit is selected an...