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Browse Prior Art Database

Test Circuit Configuration for Integrated Circuits

IP.com Disclosure Number: IPCOM000075650D
Original Publication Date: 1971-Oct-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Freed, LE: AUTHOR

Abstract

This test circuit configuration for an integrated circuit structure contains a plurality of test contacts, with which a corresponding plurality of contactors in a testing apparatus head are engaged. The test contacts re connected to testing circuits containing active and passive devises in the integrated circuit structure, in such a manner that no two adjacent contacts are in the same test circuit. This makes possible the spacing of test contacts closer than the minimal spacing required for the testing apparatus contactors to function efficiently. With such a circuit configuration, together with a sequence of at least two applications of the tester contact head to a line of test contacts, the contactor array in the test head may be more loosely spaced.

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Test Circuit Configuration for Integrated Circuits

This test circuit configuration for an integrated circuit structure contains a plurality of test contacts, with which a corresponding plurality of contactors in a testing apparatus head are engaged. The test contacts re connected to testing circuits containing active and passive devises in the integrated circuit structure, in such a manner that no two adjacent contacts are in the same test circuit. This makes possible the spacing of test contacts closer than the minimal spacing required for the testing apparatus contactors to function efficiently. With such a circuit configuration, together with a sequence of at least two applications of the tester contact head to a line of test contacts, the contactor array in the test head may be more loosely spaced. The contactor head is arranged so that on a first pass or head application a set of nonadjacent contacts in a set of testing circuits are engaged, followed by a second pass in which nonadjacent contacts in a set of testing circuits are engaged which were not previously engaged by the tester contact head. An additional advantage of such a test circuit configuration and test system is that even when a contactor is so relatively wide that it shorts across the space between two adjacent contacts, there is no effect, since the two contacts are not in the same circuit, and the adjacent contact is in a circuit which is not otherwise contacted on the particular pass and is, therefore, in a floating mode which will not effect the circuits being tested.

The figure shows a chip 10 together with one of its horizontal kerfs 12 and vertical kerfs 11. With respect to the test circuit configuration in the vertical kerf 11, it comprises two testing circuits. The first testing circuit which is designated as the "even circuit" comprises alternate test contact pads 30, 32, 36,...