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Dynamic Address Translation (DAT) for Multiprocessing System

IP.com Disclosure Number: IPCOM000075657D
Original Publication Date: 1971-Oct-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Spruth, W: AUTHOR

Abstract

Processing units (PU) employ 32-bit virtual addresses divided into a segment, a page, and a byte part. To translate virtual addresses pointing to the total large addressing capability into physical addresses of the smaller main store (MS), the segment part identifying a particular task addresses one location in a segment table containing the origin address of a page table. The page part addresses one location in the page table containing the high-order part of the physical MS address, which is combined with the low-order byte part to give the physical address. Thus, three MS cycles are required for translation.

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Dynamic Address Translation (DAT) for Multiprocessing System

Processing units (PU) employ 32-bit virtual addresses divided into a segment, a page, and a byte part. To translate virtual addresses pointing to the total large addressing capability into physical addresses of the smaller main store (MS), the segment part identifying a particular task addresses one location in a segment table containing the origin address of a page table. The page part addresses one location in the page table containing the high-order part of the physical MS address, which is combined with the low-order byte part to give the physical address. Thus, three MS cycles are required for translation.

To eliminate most of this overhead, a 256 word high-speed address translation memory (ATM) is provided for each of, for example, 16 PU's.

Whenever a PU accesses MS, it puts its own address on a 4-bit processing unit identification bus which forms part of the system bus. Main store control contains the 16 register "segment origin address local store" which comprises 1 segment origin register for each PU. MS itself contains in each virtual memory a corresponding segment address table :. and a number of page address tables. -.

The PU addresses one of the 16 ATM's. During each addressing cycle, :. the page address field of the virtual address addresses one of the 256 -. words in the ATM associated with the respective PU. The word thus retrieved contains the translated address, together with the origi...