Browse Prior Art Database

Semiconductor Storage Cell

IP.com Disclosure Number: IPCOM000075659D
Original Publication Date: 1971-Oct-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Baitinger, U: AUTHOR [+3]

Abstract

This storage cell uses highly ohmic load elements having the same structure as field-effect transistors, but no gate electrode. Between the two highly doped zones a highly ohmic channel is formed, caused by charges in the superimposed isolation layer. The load elements can be made simultaneously with field-effect transistors without additional procedural steps.

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Semiconductor Storage Cell

This storage cell uses highly ohmic load elements having the same structure as field-effect transistors, but no gate electrode. Between the two highly doped zones a highly ohmic channel is formed, caused by charges in the superimposed isolation layer. The load elements can be made simultaneously with field-effect transistors without additional procedural steps.

The storage cell contains two storage field-effect transistors 1 and 2, two input/output field-effect transistors 3 and 4, as well as two highly ohmic load resistors 5 and 6. Writing and reading is performed by addressing via bit lines BL 1, BL 2, and word line WL. The series arrangement of transistor 1 or 2, respectively, and of resistor 5 or 6, respectively, lies between potential +V and the lower potential of line GL. Similarly to the transistors, resistors 5 and 6 show spaced, highly doped zones 7 and 8 in a silicon substrate 9 which is of opposite and lower doping. Zones 7 and 8 are connected to the two external connections. On substrate 9, there is a SiO(2) layer 10 obtained by oxidation of the silicon. As in the field-effect transistors, this layer is much thinner above the range between zones 7 and 8 than above the remaining ranges of substrate 9. SiO(2) layer 10 holds relatively few positive charges which are not sufficient to form a conductive channel between zones 7 and 8. Over layer 10 of thermic SiO(2), a layer 11 of sputtered SiO(2) is provided containing, relativel...