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Slow Cooling to Minimize Distortion in Vertical Batch Processing of Large Wafers

IP.com Disclosure Number: IPCOM000075676D
Original Publication Date: 1971-Oct-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Grochowski, EG: AUTHOR [+4]

Abstract

Large-diameter wafer batches subjected to high-temperature oxidation cycles, coupled with an increase in mass, exhibit substantial thermal gradients when cooled by conventional methods, i.e., when they are pulled directly from the furnace hot zone to room atmosphere at a cooling rate of 76 degrees C/second. Excessive thermal gradients result in crystallographic stress damage and, if extreme, will cause wafer distortion. The distortion is particularly damaging if the wafer isotherms are closed loops in the plane of the wafer rather than curves, which extend across the plane of the wafer. This happens whenever a hot portion of the wafer is surrounded by a cooler region of as little as 1 degree C, as may occur during wafer withdrawal, when heat loss from the edge of the wafers exceeds that of the center portion of the wafers.

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Slow Cooling to Minimize Distortion in Vertical Batch Processing of Large Wafers

Large-diameter wafer batches subjected to high-temperature oxidation cycles, coupled with an increase in mass, exhibit substantial thermal gradients when cooled by conventional methods,
i.e., when they are pulled directly from the furnace hot zone to room atmosphere at a cooling rate of 76 degrees C/second. Excessive thermal gradients result in crystallographic stress damage and, if extreme, will cause wafer distortion. The distortion is particularly damaging if the wafer isotherms are closed loops in the plane of the wafer rather than curves, which extend across the plane of the wafer.

This happens whenever a hot portion of the wafer is surrounded by a cooler region of as little as 1 degree C, as may occur during wafer withdrawal, when heat loss from the edge of the wafers exceeds that of the center portion of the wafers. The distortion will result in poor mask resolution in subsequent photo-resist operations.

A slow-cooling cycle achieved by a controlled mechanical withdrawal system, whose withdrawal rate is determined by the slope of the furnace temperature profile, can eliminate the thermal gradients seen by the wafer surfaces. Flatness tests and scanning oscillating topographs have shown that a cooling rate of 1 degree C/second is optimum.

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