Browse Prior Art Database

Associative Memory Cell

IP.com Disclosure Number: IPCOM000075690D
Original Publication Date: 1971-Nov-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Repchick, DP: AUTHOR [+3]

Abstract

This monolithic associative memory cell can be nondestructively read both for associative searching and conventional readout. At any one time, either transistor T3 or transistor T4 is conducting. When T3 conducts, it represents a 1 stored in the cell. When T4 conducts, it represents a 0 stored in the cell. In quiescent operation, transistor T5 is biased nonconducting by a down condition on word line WL connected to its base. Thus T1 and T2 are normally held off.

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Associative Memory Cell

This monolithic associative memory cell can be nondestructively read both for associative searching and conventional readout. At any one time, either transistor T3 or transistor T4 is conducting. When T3 conducts, it represents a 1 stored in the cell. When T4 conducts, it represents a 0 stored in the cell. In quiescent operation, transistor T5 is biased nonconducting by a down condition on word line WL connected to its base. Thus T1 and T2 are normally held off.

To nondestructively read information out of the cell, WL is pulsed positive, thus biasing T5 on and causing either T1 or T2 to conduct. If T3 is conducting, T2 conducts and provides input signals to the sense amplifier. If T4 is conducting, T1 conducts and no input is provided to the sense amplifier. Therefore, this cell sends a signal to the sense amplifier only when there is a 1 stored in the cell.

To write information into the cell, WL is again biased positive so as to bias T5 conducting. Simultaneously, one bit line B0 or B1 is pulsed positive to store a 1. B0 is pulsed positively to store a 0. B1 is pulsed positively to store a 1.

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