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Fast NDRO Memory Circuits for Integration

IP.com Disclosure Number: IPCOM000075694D
Original Publication Date: 1971-Nov-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Moore, RD: AUTHOR [+2]

Abstract

The memory cell described on pages 1851 and 1852 of the May 1966 issue of the IBM Technical Disclosure Bulletin can be improved by the addition of resistor R between the emitters and ground of the cross-coupled transistors. In the article referred to, the emitters of the cross-coupled transistors in the trigger circuit are connected directly to ground. By raising the emitters above ground with resistor R, two improvements in the operating characteristics of the circuit are obtained. First, the speed of the operation of the cell is increased. Secondly, the amount of current used to switch the trigger circuit from one of its states to the other is reduced.

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Fast NDRO Memory Circuits for Integration

The memory cell described on pages 1851 and 1852 of the May 1966 issue of the IBM Technical Disclosure Bulletin can be improved by the addition of resistor R between the emitters and ground of the cross-coupled transistors. In the article referred to, the emitters of the cross-coupled transistors in the trigger circuit are connected directly to ground. By raising the emitters above ground with resistor R, two improvements in the operating characteristics of the circuit are obtained. First, the speed of the operation of the cell is increased. Secondly, the amount of current used to switch the trigger circuit from one of its states to the other is reduced.

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