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Gated Farber Memory Cell

IP.com Disclosure Number: IPCOM000075700D
Original Publication Date: 1971-Nov-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Davis, DE: AUTHOR

Abstract

This circuit reduces the amount of power dissipated by storage cells, by powering them at one level when they are interrogated and at another level when they are not being interrogated.

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Gated Farber Memory Cell

This circuit reduces the amount of power dissipated by storage cells, by powering them at one level when they are interrogated and at another level when they are not being interrogated.

Cross-coupled transistors T2 and T3 form a bistable circuit which stores one bit of binary information. The binary stored depends upon whether T2 or T3 is conducting. While the circuit is not being addressed for reading or writing information, the bistable circuit is powered by sources V1 end V2. This power is sufficient to maintain the state stored in the bistable circuit. That is, the collector current of the conducting transistor in the bistable circuit is sufficient to guarantee the off transistor in the bistable circuit remains off. However, the amount of power supplied to the bistable circuit is not sufficient when the bistable circuit is addressed for reading or writing. Therefore, additional power is supplied to the circuit through resistor R5 when the cell is addressed for reading or writing. This is accomplished by turning transistor T5 on with the proper X and Y selection voltages at its base and emitter, respectively. When T5 conducts its collector current is divided into a set proportion between resistors R4 and R5. With increased power supplied through R5 the reading and writing functions may be performed.

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