Browse Prior Art Database

Bilevel Power Storage Cell

IP.com Disclosure Number: IPCOM000075702D
Original Publication Date: 1971-Nov-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

McDowell, JJ: AUTHOR

Abstract

This circuit provides two levels of voltage to a monolithic memory cell to reduce the amount of power dissipated by the cell.

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Bilevel Power Storage Cell

This circuit provides two levels of voltage to a monolithic memory cell to reduce the amount of power dissipated by the cell.

Cross-coupled transistors T2 and T3 form a bistable circuit which stores one bit of binary information. While the circuit is not being addressed for reading or writing information, the level of excitation supplied to this bistable circuit depends on the divider action of resistors R4 and R5. This level should be the lowest value that will retain information in the trigger circuit. However, when the circuit is being addressed for reading or writing more power is needed. Thus when the X and Y terminals are addressed for reading, transistor T7 is turned on by the signal supplied to the Y terminal. This clamps the node between resistors R4 and R5 to V1, thereby increasing the level of the excitation supplied to the bistable circuit to a value which will allow reading or writing information in the cell.

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