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Browse Prior Art Database

Addressing an Array of Multiemitter Storage Cells

IP.com Disclosure Number: IPCOM000075703D
Original Publication Date: 1971-Nov-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Tertel, K: AUTHOR

Abstract

This addressing scheme permits X-Y addressing of a multiple emitter cell.

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Addressing an Array of Multiemitter Storage Cells

This addressing scheme permits X-Y addressing of a multiple emitter cell.

Cross-coupled transistors T3 and T4 form a bistable circuit which stores one bit of information. The bit of information stored depends on whether T3 or T4 is conducting. While the cell is not being addressed either T1 or T2 is conducting causing the emitters e2 and e3 to be lower in potential than the emitters e1 and e4. Thus the current flowing through the double-emitter transistor flows through either emitter e2 or e3. However, when the cell is addressed with proper X and Y addressing currents both T1 and T2 are turned off, allowing the voltage at the emitters e2 and e3 to rise above the voltages at the emitters e1 and e4, causing the current flowing through either emitter e2 or e3 to switch to either emitter e1 or e4, respectively, to provide an output signal to be sensed by a sense amplifier.

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