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Schottky Barrier Diode Storage Cell

IP.com Disclosure Number: IPCOM000075706D
Original Publication Date: 1971-Nov-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 23K

Publishing Venue

IBM

Related People

Moore, RD: AUTHOR

Abstract

By employing Schottky barrier diodes D1 and D2 as the load elements for transistors T1 and T2, the standby potential supplied to word line WL can be reduced and bistable operation is assured.

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Schottky Barrier Diode Storage Cell

By employing Schottky barrier diodes D1 and D2 as the load elements for transistors T1 and T2, the standby potential supplied to word line WL can be reduced and bistable operation is assured.

With the storage cell operating, one transistor T1 or T2 is conducting and the other transistor is held off by the cross coupling between them. In order to insure bistability for the storage cell, i.e., to insure that one transistor is held off while the other is conducting, it is necessary that the dynamic impedance of D1 or D2 be greater than the dynamic impedance of the base emitter junctions of T1 and T2. While this is difficult using diffused diodes and transistors, it is easily accomplished when Schottky barrier diodes are employed in conjunction with diffused transistors. The transistors are made using standard planar techniques and the Schottky diodes D1 and D2 are then fabricated by placing metalization patter a in contact with both the collector diffusions of T1 and T2.

While the storage cell is not being interrogated for reading and writing, the potential on line WL is such that the current through D1 and D2 biases these in a high impedance state. Current then flows through resistor R to bias the emitters e2 and e3 below the potential supplied to bit lines B0 and B1, so as to bias the emitters el and e4 nonconducting. When the storage cell is being interrogated, the potential on line WL is raised increasing the potential drop ac...