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Browse Prior Art Database

Storage Cell with Single Bit Line

IP.com Disclosure Number: IPCOM000075715D
Original Publication Date: 1971-Nov-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Moore, RD: AUTHOR

Abstract

The drawing shows a transistor storage cell and wires 2, 3 and 4 that connect rows and columns of the cells in a storage array. Two transistors are cross connected to form the storage cell, and one or the other of the transistors conducts, as the numbers 1 and 0 in the drawing signify, to store a 1 or a 0. A transistor 5 is connected to conduct between the collector terminal of the 1 transistor and line 4, according to the potential of line 4 and the potential at the collector terminal of the 1 transistor.

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Storage Cell with Single Bit Line

The drawing shows a transistor storage cell and wires 2, 3 and 4 that connect rows and columns of the cells in a storage array. Two transistors are cross connected to form the storage cell, and one or the other of the transistors conducts, as the numbers 1 and 0 in the drawing signify, to store a 1 or a 0. A transistor 5 is connected to conduct between the collector terminal of the 1 transistor and line 4, according to the potential of line 4 and the potential at the collector terminal of the 1 transistor.

For a read or a write operation, line 2 is raised from 1.0 volt to 2.5 volts and line 3 is raised from 0.2 volt to 1.0 volt. Terminal 6 of line 4 remains at 2 volts. When the 1 transistor is on during a read operation, the increased voltage drop across the collector resistor causes transistor 5 to conduct in its inverse mode and to draw current from line 4. Thus, a negative going voltage on line 4 signifies a stored 1. When a 0 is stored, the collector potential of the 1 transistor is higher than the potential of line 4 and transistor 5 remains off. Thus, the absence of a signal on line 4 signifies a stored 0.

To write a 0, line 4 is made positive to turn on the 0 transistor. To write a 1, line 4 is made negative to turn off the 0 transistor and thereby allow the 1 transistor to turn on.

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