Browse Prior Art Database

Three State Storage Cell

IP.com Disclosure Number: IPCOM000075716D
Original Publication Date: 1971-Nov-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Fugere, DG: AUTHOR [+2]

Abstract

The storage cell of the drawing is connectable at terminals 2 and 3 to a pair of bit-sense wires for the corresponding bit position of a memory array. A terminal 4 is connectable to a word wire for receiving signals to select cells of an addressed word for read and write operations. Transistors 5 and 6 form a bistable circuit to provide a first storage state when transistor 5 is conducting and a second storage state when transistor 6 is conducting. Transistors 7, 8 and 9 control transistors 5 and 6 to provide a third storage state in which both transistors 5 and 6 are off.

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Three State Storage Cell

The storage cell of the drawing is connectable at terminals 2 and 3 to a pair of bit-sense wires for the corresponding bit position of a memory array. A terminal 4 is connectable to a word wire for receiving signals to select cells of an addressed word for read and write operations. Transistors 5 and 6 form a bistable circuit to provide a first storage state when transistor 5 is conducting and a second storage state when transistor 6 is conducting. Transistors 7, 8 and 9 control transistors 5 and 6 to provide a third storage state in which both transistors 5 and 6 are off.

To write either the first or second storage state into the cell, coincident signals are applied to terminal 4 and to either terminal 2 or terminal 3 to turn on one transistor 5 or 6 and turn off the other transistor. When either transistor 5 or 6 is on, one of the emitter terminals of transistor 8 is lowered sufficiently to turn off transistor 9. When transistor 9 is off, transistor 7 is on to permit one of transistors 5 and 6 to conduct.

To write the third storage state into the cell, a signal is applied to terminal 4 to turn off transistor 10 and thereby turn off both transistors 5 and 6. Transistor 9 turns on and transistor 7 turns off and prevents either transistor 5 or 6 from turning on, when the potential at terminal 4 is raised at the end of the write operation.

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