Browse Prior Art Database

Four State Memory Cell

IP.com Disclosure Number: IPCOM000075717D
Original Publication Date: 1971-Nov-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Fugere, DG: AUTHOR [+2]

Abstract

The drawing shows a storage cell which provides four stable states. Pairs of double-emitter transistors 2, 3 and 4, 5 are cross connected as binary storage cells. Emitter terminals 6 and 7 are connected to reference potential points. Emitter terminals 8 and 9 are connected to individual bit-sense wires that similarly connect to other storage cells of the same bit position of the memory. The other emitter terminal of each transistor is connected to the collector terminal of a transistor 12 that is controlled from a terminal, 13 to address the cell for read and write operations.

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Four State Memory Cell

The drawing shows a storage cell which provides four stable states. Pairs of double-emitter transistors 2, 3 and 4, 5 are cross connected as binary storage cells. Emitter terminals 6 and 7 are connected to reference potential points. Emitter terminals 8 and 9 are connected to individual bit-sense wires that similarly connect to other storage cells of the same bit position of the memory. The other emitter terminal of each transistor is connected to the collector terminal of a transistor 12 that is controlled from a terminal, 13 to address the cell for read and write operations.

For a write operation, transistor 12 is turned off to thereby cause the transistors to operate according to the potential at the emitter terminals 6, 7, 8 and 9. Potentials are applied to the bit-sense terminals 8, 9 according to the state to which the cells are to be set, and transistor 12 is then turned on again to switch the operation of the conducting transistors to the emitter terminals that conduct in circuit with transistor 12. For example, when transistor 12 turns off, transistors 2 and 5 turn on and conduct in circuit with emitter terminals 6 and 7. When a more negative potential is applied to bits sense terminal 8, transistor 3 turns on and transistor 2 turns off.

For a read operation, transistor 12 is turned off to switch conduction from the associated emitter terminals to the emitter terminals 6 or 8 and 7 or 9 of the conducting transistor. When transistor...