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Antisaturation Arrangement for Multiemitter Storage Cells

IP.com Disclosure Number: IPCOM000075718D
Original Publication Date: 1971-Nov-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Wiedmann, SK: AUTHOR

Abstract

By connecting one emitter in each of the cross connected transistors T1 and T2 to the base of the transistor T1 or T2 deep saturation can be avoided.

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Antisaturation Arrangement for Multiemitter Storage Cells

By connecting one emitter in each of the cross connected transistors T1 and T2 to the base of the transistor T1 or T2 deep saturation can be avoided.

Harper patent No. 3,423,737 discloses a storage cell employing two cross connected double emitter transistors. When a third emitter E III is added to each transistor and is shorted to the base of the transistor, as has been done in the case of transistors T1 and T2, deep saturation can be avoided. The reduction in saturation is a result of parasitic current flowing into the reverse-biased emitter E III of the on transistor T2, due to inverse transistor action.

The additional emitters E III take up very little space when the storage cell is fabricated in monolithic form, since the same contact hole can be used for the base B and for the third emitter E III of both transistors T1 and T2.

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