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Monolithic Associative Memory Using Read/Write Array

IP.com Disclosure Number: IPCOM000075719D
Original Publication Date: 1971-Nov-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Lohrey, FH: AUTHOR [+3]

Abstract

This memory cell stores a bit of information that can be associatively searched.

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Monolithic Associative Memory Using Read/Write Array

This memory cell stores a bit of information that can be associatively searched.

With a "1" stored in the storage cell transistors T1 and T4 are conducting and transistors T2 and T3 are off. If a "0" is stored in the storage cell transistors T2 and T3 would be conducting and transistors T1 and T4 would be off.

Assume that a 1 is stored in the storage cell and the storage cell is associatively searched for a 1 by application of a positive pulse to the 1 bit line. Then there would be no output on the sense and write A line because transistor T5 will be held off by the conducting transistor T1. Since there is no pulse, the output of the sense amplifier would indicate a match. If a 0 had been stored in the storage cell transistor T5 would conduct, providing an output signal on the sense and write A line, thereby providing a no-match output from the sense amplifier.

Interrogation for a 0 operates in the same way, except an interrogation pulse is applied to the 0 bit line.

To write a 1 into the storage cell, the 1 bit line is driven positive and the write A line is driven negative. Transistor T5 then conducts turning transistor T1 on. Then the 0 bit line is driven positive and the write B line is driven negative, causing transistor T8 to conduct and turn transistor T4 on. The result is then that transistors T1 and T4 are on and a 1 is stored.

To read the information stored in the cell the 0 bit line is driven positiv...